1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a BiCMOS circuit as a combination of a CMOS gate and a bipolar transistor.
2. Description of the Related Art
The BiCMOS circuit has two advantageous features; a low power dissipation as the feature of the CMOS circuit and a high drivability as the feature of the bipolar transistor. Because of these features, the BiCMOS circuits have been used in a variety of circuits, such as gate arrays, logic ICs, high speed SRAM and high speed DRAM.
FIG. 22 is a circuit diagram of a BiCMOS inverter, which is a basic arrangement of the BiCMOS circuit. As shown, the inverter is made up of a CMOS inverter 1, a charge circuit 2, and a discharge circuit 3. The charge circuit 2 is coupled between an output node of the inverter 1 and an output terminal B. The discharge circuit 3 allows the output node B to be discharged. The inverter 1 consists of a p-channel MOS transistor M1 and an n-channel MOS transistor M2, both transistors being interconnected at the drains. The charge circuit 2 consists of a first npn bipolar transistor Q1 whose collector is connected to a high potential source Vcc, base is connected to the output node A of the inverter 1, and emitter is connected to the output terminal B. The discharge circuit 3 consists of a second npn bipolar transistor Q2, and a couple of n-channel MOS transistors M3 and M4 for controlling the transistor Q2. The transistors Q1 and Q2 are connected in a totem pole fashion between the high potential source Vcc and a low potential source Vss. The source--drain path of the transistor M3 is connected between the output terminal B and the base of the transistor Q2. The transistor M3 receives at the gate an input signal Vin that is for the inverter 1, and operates under control of the signal Vin. In accordance with the input signal Vin, the transistor M3 forms a short-circuit between the collector and the base of the transistor Q2. In other words, the transistor M3 serves as an on-drive MOS transistor, which transfers a potential at the emitter of the first npn bipolar transistor Q1 to the base of the second npn bipolar transistor Q2, and turns on the transistor Q2. The source--drain path of the transistor M4 is connected between the base of the bipolar transistor Q2 and the source Vss of low potential. The transistor M4 receives at the gate a potential at the output node A of the CMOS inverter 1, and operates under control of that potential. In accordance with the output potential of the inverter 1, the transistor M4 provides a path through which charges at the base of the bipolar transistor Q2 flow to the source Vss. In this sense, the transistor M4 serves as an off-drive MOS transistor for turning off the transistor Q2.
The waveforms shown in FIG. 23 are useful in explaining the operation of the BiCMOS inverter. The waveforms were plotted under the condition that Vcc=5V, Vss=0V, and the input signal Vin was a clock signal of 5V in amplitude. When the input signal Vin is pulsed from a high of 5V to a low of 0V, the output node A of the CMOS inverter 1 is charged up to Vcc (=5V) through the MOS transistor M1. In turn, the bipolar transistor Q1 of the charge circuit 2 is turned on, the on-drive transistor M3 is turned off, and the off-drive transistor M4 is turned on. Under this condition, the base charge of the bipolar transistor Q2 is removed through the MOS transistor M4, turning off the transistor Q2. Consequently, the output signal Vout goes high.
When the input signal Vin goes high, the output node A goes low to turn off the transistor Q1. At this time, the transistor M3 is turned on, and the transistor M4 is turned off. Accordingly, the potential at the output terminal B is transferred to the base of the transistor Q2. The output signal Vout goes low.
In the BiCMOS inverter thus operating, the high level of the output signal Vout peaks at about 4.3V, below 5V of the Vcc, as shown in FIG. 23. The reason for this is that even where the base potential of the transistor Q1 is 5V, the transistor Q1 will turn off when the voltage between the base and the emitter of it is below the built-in voltage (VBE=0.7V). FIG. 23 also shows that the low level of the output signal Vout is not 0V but about 0.7V. The reason for this is that the transistor Q2 is turned on while it is diode connected, and the on-voltage is limited by the built-in voltage VBE between the base and the emitter of it.
As seen from the graph of FIG. 23, in the conventional BiCMOS inverter, when the input signal Vin of the full swing is applied, the high level and the low level of the output signal Vout do not go to the preset levels, respectively. In the BiCMOS inverters connected in a cascade fashion, the output signal of such levels adversely affects the operations of the second stage of the BiCMOS inverter and the succeeding ones. Firstly, a through-current flows in the CMOS inverter of the second stage of the BiCMOS inverter due to the nonuniformity in the threshold values of the MOS transistors used. Consider a circuit consisting of two stages of BiCMOS inverters. In the circuit, the threshold values (absolute values) of the n- and p-channel MOS transistors in the CMOS inverter are Vth and equal to each other. When Vth&gt;VBE, the operation of the circuit is normal when the swing range of the output signal of the first stage inverter, i.e., the input signal of the second stage inverter, is VBE to Vcc - VBE. When Vth&lt;VBE, both the p- and n- channel MOS transistors are always in an on state. Accordingly, a through-current flows in the CMOS inverter, resulting in an increase of a power dissipation in a standby mode. Secondly, an impact ionization occurs in the CMOS inverter in the second stage inverter. The reason why the impact ionization occurs is that when the input signal to the second stage inverter is in a low level, a high voltage is applied across the source--drain path of the n-channel MOS transistor before its turn-off is completed. When the input signal to the second stage inverter is in a high level, the impact ionization occurs in the p-channel MOS transistor for the same reason. The impact ionization possibly has adverse effects on the characteristics of the MOS transistors, such as change of the threshold values of the MOS transistors. Further, the impact ionization increases the substrate current. Accordingly, where a substrate bias generator circuit is mounted on the chip, the load to the bias generator circuit is large and its circuit design is intricate, if the impact ionization occurs.
The above problems exist not only in the BiCMOS inverter whose input stage consists of a CMOS inverter, but also in the BiCMOS inverter whose input stage uses a NAND gate or a NOR gate.